EWM103-WF7621A Module de passerelle de routage Gigabit prenant en charge plusieurs interfaces de communication PCle/USB/I2C/SPI/RGMII/MII
[Solution de puce]：MT7621A
[Fréquence de fonctionnement]： 2,4 GHz
[Tension de fonctionnement]： 3,3 V
[Taille du produit]： 50*50*3mm
[Poids du produit]：11,1 g ± 0,2 g
[Introduction]：Le module routeur sans fil EWM103-WF7621A est une passerelle de routage Gigabit développée par Chengdu EBB autour de la puce MediaTek MT7621A. Ce module intègre un processeur double cœur MIPS-1004Kc (880 MHz), un accélérateur HNAT/HQoS/Samba/VPN et un commutateur GbE à 5 ports. Compatible avec le système d'exploitation OpenWrt et les développements personnalisés, il offre une interface riche et un processeur puissant, et peut être largement utilisé dans les appareils intelligents ou les applications de services cloud, permettant ainsi un développement secondaire aisé.
Magasin officiel
| Serial number | Pin Name | Pin Function Description | Default functionality |
| 1 | 3.3VD | power supply | - |
| 2 | 3.3VD | power supply | - |
| 3 | 3.3VD | power supply | - |
| 4 | 3.3VD | power supply | - |
| 5 | GND | land | - |
| 6 | GND | land | - |
| 7 | GND | land | - |
| 8 | GND | land | - |
| 9 | CTS3_N | UART Clear To Send | - |
| 10 | TXD2 | UART TX Data | - |
| 11 | RXD2 | UART RX Data | - |
| 12 | TXD3 | UART TX Data | - |
| 13 | RXD3 | UART RX Data | - |
| 14 | RTS2_N | UART Request To Send | - |
| 15 | CTS2_N | UART Clear To Send | - |
| 16 | RTS3_N | UART Request To Send | - |
| 17 | USB_DP_1P | USB Port1 data pin Data+ (USB2.0) | - |
| 18 | USB_DM_1P | USB Port1 data pin Data- (USB2.0) | - |
| 19 | GND | land | - |
| 20 | SSUSB_TXP | USB Port0 SS data pin TX+ (USB3.0) | - |
| 21 | SSUSB_TXN | USB Port0 SS data pin TX- (USB3.0) | - |
| 22 | SSUSB_RXP | USB Port0 SS data pin RX+ (USB3.0) | - |
| 23 | SSUSB_RXN | USB Port0 SS data pin RX+-(USB3.0) | - |
| 24 | GND | land | - |
| 25 | USB_DP_P0 | SB Port0 HS/FS/LS data pin Data+ (USB3.0) | - |
| 26 | USB_DM_P0 | USB Port0 HS/FS/LS data pin Data- (USB3.0) | - |
| 27 | GND | land | - |
| 28 | ESW_TXVP_A_P0 | Port #0 MDI Transceivers | - |
| 29 | ESW_TXVN_A_P0 | Port #0 MDI Transceivers | - |
| 30 | ESW_TXVP_B_P0 | Port #0 MDI Transceivers | - |
| 31 | ESW_TXVN_B_P0 | Port #0 MDI Transceivers | - |
| 32 | ESW_TXVP_C_P0 | Port #0 MDI Transceivers | - |
| 33 | ESW_TXVN_C_P0 | Port #0 MDI Transceivers | - |
| 34 | ESW_TXVP_D_P0 | Port #0 MDI Transceivers | - |
| 35 | ESW_TXVN_D_P0 | Port #0 MDI Transceivers | - |
| 36 | ESW_TXVP_A_P1 | Port #1 MDI Transceivers | - |
| 37 | ESW_TXVN_A_P1 | Port #1 MDI Transceivers | - |
| 38 | ESW_TXVP_B_P1 | Port #1 MDI Transceivers | - |
| 39 | ESW_TXVN_B_P1 | Port #1 MDI Transceivers | - |
| 40 | ESW_TXVP_C_P1 | Port #1 MDI Transceivers | - |
| 41 | ESW_TXVN_C_P1 | Port #1 MDI Transceivers | - |
| 42 | ESW_TXVP_D_P1 | Port #1 MDI Transceivers | - |
| 43 | ESW_TXVN_D_P1 | Port #1 MDI Transceivers | - |
| 44 | GND | land | - |
| 45 | ESW_TXVP_A_P2 | Port #2 MDI Transceivers | - |
| 46 | ESW_TXVN_A_P2 | Port #2 MDI Transceivers | - |
| 47 | ESW_TXVP_B_P2 | Port #2 MDI Transceivers | - |
| 48 | ESW_TXVN_B_P2 | Port #2 MDI Transceivers | - |
| 49 | ESW_TXVP_C_P2 | Port #2 MDI Transceivers | - |
| 50 | ESW_TXVN_C_P2 | Port #2 MDI Transceivers | - |
| 51 | ESW_TXVP_D_P2 | Port #2 MDI Transceivers | - |
| 52 | ESW_TXVN_D_P2 | Port #2 MDI Transceivers | - |
| 53 | GND | land | - |
| 54 | ESW_TXVP_A_P3 | Port #3 MDI Transceivers | - |
| 55 | ESW_TXVN_A_P3 | Port #3 MDI Transceivers | - |
| 56 | ESW_TXVP_B_P3 | Port #3 MDI Transceivers | - |
| 57 | ESW_TXVN_B_P3 | Port #3 MDI Transceivers | - |
| 58 | ESW_TXVP_C_P3 | Port #3 MDI Transceivers | - |
| 59 | ESW_TXVN_C_P3 | Port #3 MDI Transceivers | - |
| 60 | ESW_TXVP_D_P3 | Port #3 MDI Transceivers | - |
| 61 | ESW_TXVN_D_P3 | Port #3 MDI Transceivers | - |
| 62 | GND | land | - |
| 63 | ESW_TXVP_A_P4 | Port #4 MDI Transceivers | - |
| 64 | ESW_TXVN_A_P4 | Port #4 MDI Transceivers | - |
| 65 | ESW_TXVP_B_P4 | Port #4 MDI Transceivers | - |
| 66 | ESW_TXVN_B_P4 | Port #4 MDI Transceivers | - |
| 67 | ESW_TXVP_C_P4 | Port #4 MDI Transceivers | - |
| 68 | ESW_TXVN_C_P4 | Port #4 MDI Transceivers | - |
| 69 | ESW_TXVP_D_P4 | Port #4 MDI Transceivers | - |
| 70 | ESW_TXVN_D_P4 | Port #4 MDI Transceivers | - |
| 71 | ESW_P4_LED_0 | Port #4 PHY LED indicators | - |
| 72 | ESW_P3_LED_0 | Port #3 PHY LED indicators | - |
| 73 | ESW_P2_LED_0 | Port #2 PHY LED indicators | - |
| 74 | ESW_P1_LED_0 | Port #1PHY LED indicators | - |
| 75 | ESW_P0_LED_0 | Port #0 PHY LED indicators | - |
| 76 | ESW_DTEST | Digital test | - |
| 77 | GE2_TXD3 | RGMII2 Tx Data bit #0 | - |
| 78 | GE2_TXD2 | RGMII2 Tx Data bit #2 | - |
| 79 | GE2_TXD1 | RGMII2 Tx Data bit #1 | - |
| 80 | GE2_TXD0 | RGMII2 Tx Data bit #0 | - |
| 81 | ESW_DBG_B | - | - |
| 82 | MDIO | PHY Data Management | Note: When RGMII/MII is connected to external PHY, this pin is MDIO. Otherwise it is NC. |
| 83 | MDC | PHY Clock Management | Note: When RGMII/MII is connected to external PHY, this pin is MDC. Otherwise, it is NC. |
| 84 | GE2_TXEN | RGMII2 Tx Data Valid | - |
| 85 | GE2_TXCLK | RGMII2 Tx Clock | - |
| 86 | GE2_RXD3 | RGMII2 Rx Data bit #3 | - |
| 87 | GE2_RXD2 | RGMII2 Rx Data bit #2 | - |
| 88 | GE2_RXD1 | RGMII2 Rx Data bit #1 | - |
| 89 | GE2_RXD0 | RGMII2 Rx Data bit #0 | - |
| 90 | GE2_RXDV | RGMII2 Rx Data Valid | - |
| 91 | GE2_RXCLK | RGMII2 Rx Clock | - |
| 92 | GND | land | - |
| 93 | RXD1 | UART TX Data | - |
| 94 | TXD1 | UART RX Data | - |
| 95 | PORST_N | Power-On Reset | - |
| 96 | I2C_SCLK | I2C Clock | - |
| 97 | I2C_SD | I2C Data | - |
| 98 | PCIE_TXN2 | PCIE2_TX- | - |
| 99 | PCIE_TXP2 | PCIE2_TX+ | - |
| 100 | PCIE_RXN2 | PCIE2_RX- | - |
| 101 | PCIE_RXP2 | PCIE2_RX+ | - |
| 102 | PCIE_CKN2 | PCIE2_CLK- | - |
| 103 | PCIE_CKP2 | PCIE2_CLK+ | - |
| 104 | GPIO0 | - | - |
| 105 | PRESS_N | PCIE | - |
| 106 | PCIE_TXP1 | PCIE1_TX+ | - |
| 107 | PCIE_TXN1 | PCIE1_TX- | - |
| 108 | PCIE_RXP1 | PCIE1_RX+ | - |
| 109 | PCIE_RXN1 | PCIE1_RX- | - |
| 110 | PCIE_CKN1 | PCIE1_CLK- | - |
| 111 | PCIE_CKP1 | PCIE1_CLK+ | - |
| 112 | WDT_RST_N | NC | - |
| 113 | PCIE_RXP0 | PCIE0_RX+ | - |
| 114 | PCIE_RXN0 | PCIE0_RX- | - |
| 115 | PCIE_TXN0 | PCIE0_TX- | - |
| 116 | PCIE_TXP0 | PCIE0_TX+ | - |
| 117 | PCIE_CKP0 | PCIE0_CLK+ | - |
| 118 | PCIE_CKN0 | PCIE0_CLK- | - |
| 119 | GND | land | - |
| 120 | JTMS | JTAG Mode Select | - |
| 121 | JTDO | JTAG Data Output | - |
| 122 | JTDI | JTAG Data Input | - |
| 123 | JTRST_N | JTAG Target Reset | - |
| 124 | JTCLK | JTAG Clock | - |
| 125 | GND | land | - |
| 126 | ND_D7 | NAND Flash Data7 | - |
| 127 | ND_D6 | NAND Flash Data6 | - |
| 128 | ND_D5 | NAND Flash Data5 | - |
| 129 | ND_D4 | NAND Flash Data4 | - |
| 130 | ND_D3 | NAND Flash Data3 | - |
| 131 | ND_D2 | NAND Flash Data2 | - |
| 132 | ND_D1 | NAND Flash Data1 | - |
| 133 | ND_D0 | NAND Flash Data0 | - |
| 134 | ND_RB_N | NAND Flash Ready/Busy | - |
| 135 | ND_RE_N | NAND Flash Read Enable | - |
| 136 | ND_CS_N | NAND Flash Chip Select | - |
| 137 | ND_CLE | NAND Flash Command Latch Enable | - |
| 138 | ND_ALE | NAND Flash ALE Latch Enable | - |
| 139 | ND_WE_N | NAND Flash Write Enable | - |
| 140 | ND_WP | NAND Flash Write Protect | - |