E101-S3WN8-PS Module WiFi ble double cœur
[Solution de puce]：ESP32-S3
[Fréquence de fonctionnement]：2,4 GHz
[Distance de communication]：200 m
[Type d'interface]：E/S UART
[Protocole pris en charge]：802.11 b/g/n + BLE5.0
[Poids du produit]：2.2±0.1g
[Introduction]：E101-S3WN8-PS est un module sans fil Wi-Fi + ble dual-core universel basse consommation. Convient à une variété de scénarios d'application dans le domaine AIoT, tels que la détection de mots de réveil et la reconnaissance de commandes vocales, la détection et la reconnaissance de visages, la maison intelligente, etc. Ce module WiFi ble double cœur utilise une antenne PCB intégrée. Wi-Fi et ble cohabitent et partagent la même antenne.
Absolute maximum ratings
| Symbol | Parameter | Minimum value | Maximum value | Unit |
| VDD33 | Power pin voltage | –0.3 | 3.6 | V |
| TSTORE | storage temperature | –40 | 85 | °C |
Recommended working conditions
| Symbol | Parameter | Minimum value | Typical value | Maximum value | Unit |
| VDD33 | Power pin voltage | 3 | 3.3 | 3.6 | V |
| IVDD | Supply current from external power supply | 0.5 | — | — | A |
| T | Recommended operating temperature | –40 | — | 85 | °C |
| Humidity | humidity | — | 85 | — | %RH |
DC electrical characteristics (3.3V, 25℃)
| Symbol | Parameter | Minimum value | Typical value | Maximum value | Unit |
| CIN | Pin capacitance | — | 2 | — | pF |
| VIH | High level input voltage | 0.75×VDD1 | — | VDD1 + 0.3 | V |
| VIL | low level input voltage | –0.3 | — | 0.25×VDD1 | V |
| IIH | High level input current | — | — | 50 | nA |
| IIL | Low level input current | — | — | 50 | nA |
| VOH2 | High level output voltage | 0.8×VDD1 | — | — | V |
| VOL2 | Low level output voltage | — | — | 0.1×VDD1 | V |
| IOH | High level current source (VDD1= 3.3V,VOH>=2.64V,PAD_DRIVER=3) | — | 40 | — | mA |
| IOL | Low level current sink (VDD1=3.3 V, VOL=0.495 V, PAD_DRIVER=3) | — | 28 | — | mA |
| RP U | Internal weak pull-up resistor | — | 45 | — | kΩ |
| RP D | Internal weak pull-down resistor | — | 45 | — | kΩ |
| VIH_nRST | Chip reset release voltage (EN pin should meet the voltage range) | 0.75×VDD1 | — | VDD1 +0.3 | V |